Traditional Dual In-Line Memory Modules (DIMMs) include a multitude of Dynamic Random Access Memory (DRAM) elements carried on a signal substrate. The individual DRAM elements connect to signal lines that lead to the memory controller, allowing the individual DRAM elements to receive data from and transmit data to the memory controller.
The DIMM can also receive a clock signal from the host processor. The clock signal is then passed within the DIMM to each of the DRAM elements. The clock signals help guide the DRAM elements when to send data or when to expect to receive data (as such operations occur according to a pre-determined schedule, such as the leading or trailing edge of the clock signal).
But even though DIMMs are not large and signals travel at nearly the speed of light, signals still take a measurable amount of time to travel along the DIMM. Recall that light takes approximately one nanosecond (1 ns) to travel one foot. With computers performing billions of operations per second, even small amounts of time can make a difference in how a DIMM operates. Different DRAM elements can receive their signals at different times: that is, the DRAM elements receive staggered signals. The JEDEC-defined Fly-By DIMM topology on the command/address/clock bus, combined with the application-defined board channel skew, contribute to the differing command address arrivals for which current memory controllers must account. Different DIMM designs can have different board channel skew.
Memory controllers are designed to handle a range of topology-based different arrival times and reasonable board channel skew. Memory controllers can perform training to learn exactly what the board channel skew is for a particular DIMM and interconnect to a DIMM. Different memory controllers have different limits on how much board channel skew they can tolerate. But all memory controllers expect DIMMs to have some board channel skew.
In contrast to traditional DIMMs, DIMM Solid State Drives (SSDs) do not have multiple DRAM elements. A DIMM SSD has only one chip, which stores all the data. As a result, a DIMM SSD has no command/address/clock skew: all data can be read and written at the same time. But because memory controllers expect a DIMM to have some byte/nibble skew, more-aligned launch times for the byte/nibble lanes can introduce noise can affect the operation of the system.
A need remains for a way to permit the use of DIMM SSDs with memory controllers the expect board channel skew.